【Responsibilities】 1. Logic design and verification for SOC; 2. Simulation and System debugging; 3. FPGA/ASIC flow for synthesis, timing analysis and related debugging. 【Requirements】 1. MS in Microelectronic, Electronic Engineering, Computer Science or related; 2. Knowledge of digital circuit design, computer system architecture; 3. Familiar with Verilog or VHDL, and behavior modeling; 4. Experience with FPGA or ASIC design tools, such as Simulator, Synthesis and STA; 5. Knowledge of the following is a plus: DDR, SATA, PCIe, NVMe, Ethernet, Storage System; 6. Good team work capability with others. 月薪范围:10000-20000 元 该岗位也在 www.51job.com 和 www.zhaopin.com 发布。 搜索 威盛电子 发送简历至: ritawang@viatech.com.cn
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